i) Field of the Invention
The present invention relates generally to electro-optical transmission systems and, more particularly, to breakless electro-optical transmission systems.
ii) Description of the Prior Art
As disclosed in Japanese Patent Laid-open No. Hei 1-264426, published on Oct. 26, 1989, a conventional light transmission system is shown in FIG. 1. FIG. 1 only shows a pair of light transmission lines, but it should be appreciated that the system includes many such pairs. Only one pair is shown so as to simplify the discussion of the system. The pair of transmission lines includes a current transmission line 7 and a standby transmission line 8. The current transmission line 7 is the currently active line, and the standby line 8 is a reserve line that is used when the current transmission line is not functioning properly. The standby line 8 enhances the reliability of the system and enables the system to operate without interruption. Generally, these lines 7 and 8 are of different lengths.
A multiplexer 1 allocates input digital information strings (i.e., strings of bits) that are supplied from a plurality of terminals (such as terminal equipment or low level multiplexers) to frames that are output. A frame is a logical structure that includes digital information strings from each of the terminals. The frames are often concatenated together into logical structures known as multi-frames. Hence, the multiplexer 1 multiplexes the digital information strings into predetermined bit positions within the multi-frame. In addition, frame synchronizing bits are provided at the beginning of each frame to designate the beginning of the frame.
Each terminal is assigned a particular time slot within each frame in which it may transmit digital information strings through the multiplexer 1. The multiplexer 1 receives digital information strings from the respective terminals in a predefined sequence that cycles through all of the terminals. For instance, in each frame the multiplexer 1 may accept eight bits from every terminal in a predefined sequence. These digital information strings are inserted into specific bit positions in the multi-frame.
In addition, a long frame pattern insertion circuit 2 inserts a long frame pattern (i.e. a multi-frame I.D. that identifies the multi-frame) into vacant bit positions within the multi-frame that is output from the multiplexer 1. The circuitry for the pattern insertion circuit 2 is shown in more detail in FIG. 2. The pattern insertion circuit 2 is composed of three main components: a timing signal generator 17, a long frame pattern generator 19 and a selector 21. The timing signal generator 17 indicates the time slot in which the long frame pattern is to be inserted into the multi-frame. The timing signal generator 17 sends an appropriate signal to the selector 21 so that the selector 21 chooses, as output, either the bit train from the multiplexer 1 or a long frame pattern that is produced by the long frame pattern generator 19. The timing signal generator 17 identifies a vacant time slot into which the long frame pattern is inserted. The timing signal generator 17 may be implemented as a frame counter. The long frame pattern generator 19 is responsible for generating the long frame pattern or multi-frame I.D.
The multi-frame has a length of at least two times the maximum transmission delay difference between the current light transmission line 7 and the standby light transmission line 8. This maximum transmission delay difference is the maximum difference between the time it takes a multi-frame to travel the length of the current light transmission line 7 and the time it takes the same multi-frame to travel the length of the standby light transmission line 8. This delay is determined during initialization of the system.
A sending side transmission line selector switch 3 transmits the digital information strings 100 of the multi-frame in parallel to the current and standby light transmission lines 7 and 8, in accordance with a branching instruction fed from a sending side data link circuit 6. The branching instruction designates what information is to be transmitted over the standby transmission line 8. In particular, as mentioned above, the light transmission system of FIG. 1 includes a number of current transmission lines 7. For purposes of efficiency, a single standby line may be designated for multiple current transmission lines. There are, therefore, multiple pattern insertion circuits 2 that pass information through the switch 3. The switch 3 serves primarily as a selector which selects what information is to be transmitted over the single standby transmission line 8. As such, the switch 3 may be realized as a conventional selector mechanism that is under the control of the branching instruction.
A pair of electro-photo transducers 4 each convert the electric signals of the sending information strings 100 output from the sending side transmission line selector switch 3 into light signals and send the resulting light signals in parallel down the current transmission line 7 and the standby light transmission line 8 towards a receiving side of the system.
At the receiving side, the transmitted light signals are received from the respective current and standby light transmission lines 7 and 8 by photo-electric transducers 9. The photo-electric transducers 9 convert the light signals received from the current light transmission line 7 and the standby light transmission line 8 into electrical signals that encode respective information strings 200 and 300. In addition, the photo-electric transducers reproduce bit synchronization clock signals 400 and 500 that are received from the current transmission line 7 and standby transmission line 8, respectively. A pair of long frame synchronization circuits 12 receive the respective information strings 200 and 300 and the respective bit synchronization clock signals 400 and 500 from the photo-electric transducers 9. The long frame synchronization circuits 12 use these input signals to separate the respective long frame pulses 600 and 700 from the data, and the circuits 12 output the long frame pulses to a pair of elastic store memories 16 and to a delay circuit 17. The long frame pulses 600 and 700 are used to reset the address of the memories 16 to the starting address. These long frame pulses designate the start of a new multi-frame.
The receiving information strings 200 and 300 are sent from the respective photo-electric transducers 9 to the data lines of the elastic store memories 16 and are written into the elastic store memories 16 at consecutive memory locations. The respective bit synchronization clock signals 400 and 500 are used as writing clocks for writing the digital information strings 200 and 300 into consecutive memory locations in the elastic store memories 16. The elastic store memories should each be able to hold one multi-frame.
In order to ensure synchronization of the receiving information strings 200 and 300 between the current and standby light transmission lines 7 and 8, the long frame pulse 600 is delayed by an amount of time equal to half the long frame pattern length, in the delay circuit 17, to obtain a delayed long frame pulse 800. This illustration assumes that the transmission time for the standby line 8 is delayed relative to the transmission time for the current line by one half of a multi-frame. The receiving information strings 200 and 300 are read out of the respective elastic store memories 16, upon receiving the delayed long frame pulse 800, using the bit synchronization clock signal 400 as a reading clock.
A receiving side transmission line selector switch 10 separates the information received from the memories 16 according to a separation instruction sent from a receiving side data link circuit 14. This data link circuit 14, like the sending side data link circuit 10, is used as a line for receiving and transmitting signals. These circuits 6 and 14 include a bit separating/inserting circuit for receiving and transmitting signals via a vacant time slot in the bit train.
The sending side transmission line selector switch 3 further separates the current light transmission line 7 in accordance with the separation instruction fed from the receiving side data link circuit 14 via the sending side data link circuit 6. A multiple selector 11 separates the multiplexed information string fed from the receiving side transmission line selector switch 10 into a plurality of information strings and outputs the separated information strings to a plurality of terminals.
In the conventional light transmission system, as described above, first, the synchronization of the receiving information strings between the current and standby light transmission lines is ensured by using one of the clocks read out of the pair of elastic store memories. Once the data is read from the elastic stores, the light transmission lines are switched in accordance with a breakless transmission line switching method. However, synchronization of the breakless transmission line switching method is controlled by using clocks read out of the memory and, hence, a large memory capacity is required relative to the transmission capacity. In addition, upon failure of the current line, the system must switch to the standby line. During the transition to the standby line, transmissions are often noisy and prone to error.
It is, therefore, an object of the present invention to provide a breakless electro-optical transmission system that does not require a large memory capacity relative to its transmission capacity.
It is a further object of the present invention to reduce the noise and errors in optical transmissions in a breakless electro-optical transmission system upon failure of a currently transmitting line.